Developments in 3-D Packaging Bendigo VIC

provided by: Semiconductor International

As Joseph Fjelstad, CEO and founder of SiliconPipe (San Jose), pointed out during a presentation about advanced packaging at SEMICON West 2007, there have been three distinct eras in the evolution of electronic assembly (Figure). These eras include through hole, surface mount and chip scale. We're still at the chip-scale era with many technologies, but the new era in packaging is 3-D - although its start admittedly dates back quite a few years.

What's driving 3-D technology? "It's the need for speed and miniaturization. All good things come from making things smaller, because you reduce the amount of energy and materials needed," Fjelstad explained. "Digital electronics and telecom operating frequencies are now well into the multi-GHz range. Many CPUs are operating at 4 GHz. And while the leading-edge data rate is 10 Gb/sec, we may see it reach as high as 40 Gb/sec within the next five years. Wireless technologies are in the multi-GHz range, and more functionality is being sought at lower costs. Packaging continues to hold the key to performance in the future."

As far as interconnection challenges ahead, Fjelstad sees an interconnection gap within design approaches because there is a gap between signal speeds on ICs and signal speeds on PCBs. This gap is rapidly becoming a major technology bottleneck for electronic system performance. "We're discovering that traditional chip-based interconnect gap solutions are running out of steam - there are problems associated with signal loss, signal degradation, cross talk, reflections and power requirements," he said.

And as on-chip signal speed rises, the importance of packaging is also rising. "Design and materials are part of this performance problem, so there's a need for improved 3-D options and approaches to PCB design and interconnection to meet future system performance needs," Fjelstad said.

The approach to system design must also change. "Thinking in 3-D is a critical element going forward. It's the key to successful volumetric system miniaturization and interconnection," Fjelstad explained. "Silicon, package and PCB interconnections must now be considered concurrently in the design process. Design tools are slowly evolving to address the problem, but gaps still exist. The interconnect challenge spans the entire range of interconnections: improved IC packages, high-performance IC sockets, alternative PCB substrate design, high-performance connectors, low-attenuation backplanes and control of ESD."

What are the 3-D packaging choices? They include stacked die, stacked packages, folded package assemblies or a combination of these options.

Stacked die allows suppliers to rapidly develop basic multiple-die combinations, according to Fjelstad. "Often, two or even up to nine die are encased in a single fine-pitch BGA package outline," he said. "The most efficient die-stack package assembly process uses die combinations with a size variation that can be mounted sequentially in a pyramid fashion."

Stacked packages offer a higher-density packaging scheme that helps reduce size and I/O at board level that can also be used to create a system-in-a-package (SiP), Fjelstad said. Stacked packaging is used in flash/SRAM, DSP/flash and other applications.

Fold-over package assemblies' advantages, on the other hand, include assembling die in a planar manner without stacking. They also offer a potential reduction in size vs. other stacking solutions.

Challenges associated with 3-D packaging? "Multiple-die packages must address key logistics issues, such as being able to accommodate incompatible die shrinks; simplify management of multiple IC vendors; enable package-level test and burn-in; enable the combination of high- and low-yield devices; contribute to product quality and reliability; maximize configuration flexibility and minimize time to market; and risk, because time is our most precious commodity," Fjelstad said.

How about 3-D interconnections for 3-D packages? According to Fjelstad, 3-D interconnection structures require a perspective more akin to civil engineers who must address traffic problems to ensure smooth operation of a metropolis. He also described several ways to rethink interconnections, including one in which the connector's and PCB's electrical contacts are stair-stepped to eliminate plated through holes, and curved opposing conductors eliminate capacitive stubs and impedance disturbances.

Fjelstad stressed that copper-based interconnection technology still offers significant performance and, to capture the benefit, the IC package and system architecture must be reconsidered. "The third dimension is key not only in SiP, but also for supporting interconnections," he said.

author: Sally Cole Johnson, Contributing Editor

Semiconductor International. Copyright © 2007 Reed Business Information, a division of Reed Elsevier Inc. All rights reserved.